ASIC Design Engineer

Warsaw, Masovian Voivodeship, Poland expand job description ↓


About Plumerai

We believe autonomy and embedded intelligence will be the most impactful technologies in the next decade and the lack of an efficient deep learning platform is the main thing holding this future back. Binarized Neural Networks (BNNs) can result in a theoretical 1000x performance improvement and we believe this is the way forward. Our team is based in London and Warsaw, with a new office opening in Amsterdam. We are backed by world-class investors with strong backgrounds in deep learning and with track records of founding multi-billion dollar chip and hardware companies.

We work in the area of hardware acceleration of deep learning algorithms, our target is to run very complex computations with low power budget. We are looking for talented and ambitious Asic engineers to develop the next generation of deep learning accelerators. The work will involve a lot of design exploration and rapid prototyping. Close collaboration with our software and algorithm teams is part of the development process. This is a fantastic opportunity to learn about and contribute to the exciting field of deep learning.


  • Architecture, design, verification and validation of RTL components.
  • Board bring-up and debugging.
  • Cross-team collaboration and customer support.
  • Challenging and creative environment where contributions are highly visible. Suggestions and taking initiatives are appreciated.
  • We provide a lot of autonomy and expect our engineers to own the design from A to Z.
  • We expect our engineers to be energetic and driven to succeed because this is an opportunity to learn a lot and take on many responsibilities. Career advancement opportunities are to be expected as the company grows.


  • At least 3 years of experience in a similar role.
  • Working knowledge and experience with modern FPGA architectures, CAD tools (Vivado or Quartus) and techniques.
  • Knowledge of computer architecture. Understanding of bandwidth and latency optimisation techniques.
  • RTL and testbench development with VHDL or Verilog.
  • Familiarity with SoC architectures is desirable.
  • Knowledge of computer arithmetics.
  • Experience in hardware acceleration of mathematical algorithms.
  • System-level data exchange protocols and interconnects: AXI, AHB or others.
  • Good knowledge of hardware verification methodologies.
  • Git or similar VCS.
  • Scripting and flow automation (bash, Tcl or others).
  • Excellent spoken and written English.

Optional qualifications:

  • Linux and device driver development experience.
  • High-speed serial interfaces (Ethernet, PCIe, USB or others).
  • Advanced verification techniques (assertions, etc.) are desirable.
  • Knowledge of and/or experience with ASIC design is a plus.
  • Knowledge of parallel computing (CUDA, OpenMP) will be a plus.
  • Knowledge of ML frameworks (Tensorflow, Pytorch) will be a big plus.


  • Paid travel to top research and developer conferences.
  • Competitive base salary.
  • Choose your own laptop.
  • 25 days of paid vacation time in addition to bank holidays.
  • Flexible working hours.
  • Pension contribution.
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